1. Field of the Invention
The present invention relates to a manufacturing method for a power device having an auto-aligned double thickness gate dielectric layer and corresponding device.
The invention also relates to a power device integrated on a semiconductor substrate comprising a gate electrode formed above a channel region formed in said semiconductor substrate and insulated therefrom by means of a gate dielectric layer.
The invention particularly, but not exclusively, relates to a manufacturing method of a VDMOS power device and the following description is made with reference to this field of application for convenience of illustration only.
2. Description of the Related Art
As it is well known, the planar and vertical size decrease and the subsequent power device integration density increase involves the need to reduce the driving potentials of these devices in order to save the strength and integrity thereof. A particularly important class of silicon power devices are PowerMOSFETs which must generally meet very strict requirements in terms of minimum on state resistance and high switching speed in switching applications.
Moreover, it is important to succeed in driving these devices with very low voltages (logic or superlogic level) in order to reduce also the power consumption.
On the technological level, the need to reduce more and more a Power MOSFET operating resistance has led to a new design of the MOS capacitor structure which is formed between the gate electrode, the substrate and the gate dielectric layer interposed between these layers, and which is responsible for the switching functions themselves.
In particular, the gate dielectric layer thickness, traditionally silicon oxide, is more and more reduced in order to obtain threshold voltage values being even lower than 1 Volt without degrading excessively the breakdown strength of the diffused channel, channel which is moreover designed in order to be always as short as possible. Nevertheless, such a technological choice as the just mentioned one has some important drawbacks. In terms of switching speed, in fact, the reduction of the gate dielectric layer thickness, together with the increase in the gate electrode area being intrinsic in the higher integration density, involves lower transistor device performances because of the increased input and transition capacitive components.
Moreover, in some more and more important applications wherein the device must integrally support the action of ionized environmental agents, for example in satellites or high nuclear radiation concentration environments, an excessive reduction of the involved geometries and of the gate dielectric layer thickness can generate a considerable device weakening with respect to the action of very energetic heavy ions passing through the device and capable of depositing very high amounts of energy/charge in the active region of the device itself.
A prior art solution to meet this requirement to form thin, but radiation-resistant, gate dielectric layers, provides the integration in traditional MOS devices of gate dielectric layers being different from thermal silicon oxide (SiO2) such as for example hafnium oxide, aluminum oxide or silicon oxide/silicon nitride multilayers.
Although advantageous in many aspects, this first solution has several drawbacks connected to the use of alternative materials whose use at industrial level involves long implementation steps being subject to tests which might require prohibitive times for the present market of the devices concerned.